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INTEGRATED CIRCUITS
DATA SHEET
SAA7186 Digital video scaler
Preliminary specification File under Integrated Circuits, IC22 May 1993
Philips Semiconductors
Preliminary specification
Digital video scaler
CONTENTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION OPERATION CYCLE I2C-BUS FORMAT LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS PROCESSING DELAYS PROGRAMMING EXAMPLE PACKAGE OUTLINE SOLDERING DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
SAA7186
May 1993
2
Philips Semiconductors
Preliminary specification
Digital video scaler
1 FEATURES 2 GENERAL DESCRIPTION
SAA7186
* Scaling of video picture windows down to randomly sized windows * Processes maximum 1023 pixels per line and 1023 lines per field * Two-dimensional data processing for improved signal quality of scaled video data and for compression of video data * 16-bit YUV input data buffer * Interlace/non-interlace video data processing and field control * Line memories in Y path and UV path to store two lines, each with 2 x 768 x 8 bit capacity * Vertical sync processing by scale control * Non-scaled mode to get full picture or to gate videotext lines * UV input and output data binary/two's complement * Switchable RGB matrix and anti-gamma ROMs * 16-word FIFO register for 32-bit output data * Output formats: 5-bit and 8-bit RGB, 8-bit YUV or 8-bit monochrome
The CMOS circuit SAA7186 scales and filters digital video data to randomly sized picture windows. YUV input data in 4:2:2 format are required (SAA7191B source).
3
QUICK REFERENCE DATA SYMBOL PARAMETER supply voltage total supply current (inputs LOW, without output load) data input level data output level input clock frequency operating ambient temperature range 0 MIN. 4.5 5 TYP. MAX. 5.5 180 V mA UNIT
VDD IDD tot VI VO LLC Tamb 4
TTL-compatible TTL-compatible 32 70 MHz C
ORDERING INFORMATION EXTENDED TYPE NUMBER PACKAGE PINS 100 QFP PIN POSITION MATERIAL plastic CODE SOT317-2
SAA7186
May 1993
3
5
ARITHMETIC
HREF SCALE CONTROL
37
ARITHMETIC
May 1993
+5 V VDD1 to VDD8 5, 14, 26,40, 55, 67, 76, 91 51 VLCK VOEN BTST 50 8 OUTPUT FORMATTER OUTPUT FIFO REGISTER 48 49 output pins (1): 56 to 64 68 to 75, 77 80 to 88 92 to 100 1 2 VRO (31 to 0); 32-bit VRAM port output RGB or YUV INCADR HFL 47 RGB MATRIX Y U V VERTICAL FILTER U INTERPOLATOR V CHROMA KEYER 15 FOLLOWED 8 BY ANTI-GAMMA 8 ROMs
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VERTICAL FILTER LINE MEMORY (2x8x768)
Philips Semiconductors
BLOCK DIAGRAM
Digital video scaler
YIN (7-0)
33 to 30
Y
25 to 22
LUMINANCE DECIMATION FILTER
INPUT DATA BUFFER
20 to 17 LINE MEMORY (2x8x768)
UVIN (7-0)
13 to 10
UV
CHROMA DECIMATION FILTER
LNQ HREFD
4
VS
38
RESN
43
SCL CLOCK GENERATION 3, 16, 28, 42, 53, 65, 78, 89 35 SP AP 36 7 8 VSS1 to V
45
SAA7186
9, 15, 21, 27, 29, 39, 34, 41, 52, 54, 60, 66, 72, 79, 84, 90, 96 n.c.
2
controls
SDA
44
IC CONTROL
status
46
4, 6,
SS8
IICSA
i.c.
MEH422-1
CREF
LLC
(1) without pins 60, 72, 84 and 96, these pins are not connected
Preliminary specification
SAA7186
Fig.1 Block diagram. Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Digital video scaler
6 PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 STATUS O O - - - - I I - I I I I - - - I I I I - I I I I - - - - I I I I - I I I I - - not connected clock reference, external sync signal line-locked system clock input signal (twice of pixel rate) luminance input data (bits 4 to 7) +5 V supply voltage 3 not connected GND3 (0 V) not connected luminance input data (bits 0 to 3) not connected time-multiplexed colour-difference input data (bits 4 to 7) +5 V supply voltage 2 not connected GND2 (0 V) time-multiplexed colour-difference input data (bits 0 to 3) DESCRIPTION
SAA7186
SYMBOL LNQ HREFD VSS1 i.c. VDD1 i.c. SP AP n.c. UVIN0 UVIN1 UVIN2 UVIN3 VDD2 n.c. VSS2 UVIN4 UVIN5 UVIN6 UVIN7 n.c. YIN0 YIN1 YIN2 YIN3 VDD3 n.c. VSS3 n.c. YIN4 YIN5 YIN6 YIN7 n.c. CREF LLC HREF VS n.c. VDD4 May 1993
line qualifier signal; active polarity defined by QPL-bit in "10" (VCLK strobed) delay-compensated HREF output signal (VCLK strobed) GND1 (0 V) internally connected +5 V supply voltage 1 internally connected connected to ground (shift pin for testing) connected to ground (action pin for testing) not connected
horizontal reference, pixel data clock signal (also present during vertical blanking) vertical sync input signal (approximately 6 lines long) not connected +5 V supply voltage 4 5
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
SYMBOL n.c. VSS4 RESN SDA SCL IICSA BTST INCADR HFL VOEN VCLK n.c. VSS5 n.c. VDD5 VRO31 VRO30 VRO29 VRO28 n.c. VRO27 VRO26 VRO25 VRO24 VSS6 n.c. VDD6 VRO23 VRO22 VRO21 VRO20 n.c. VRO19 VRO18 VRO17 VDD7 VRO16 VSS7 n.c.
PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
STATUS - - I I/O I I I O O I I - - - - O O O O - O O O O - - - O O O O - O O O - O - - +5 V supply voltage 7 GND6 (0 V) not connected +5 V supply voltage 6 not connected not connected GND4 (0 V)
DESCRIPTION
reset input (active-LOW for at least 30LLC periods) IIC-bus data line IIC-bus clock line set module address input of IIC-bus (LOW = B8, HIGH = BC) output disable input; HIGH sets all data outputs to high-impedance state line increment / vertical reset control output line FIFO register half-full flag output VRAM port output enable input (active-LOW) FIFO register clock input signal not connected GND5 (0 V) not connected +5 V supply voltage 5
video output; 32-bit VRAM output port (bits 31 to 28)
video output; 32-bit VRAM output port (bits 27 to 24)
video output; 32-bit VRAM output port (bits 23 to 22) video output; 32-bit VRAM output port (bits 21 to 20) not connected video output; 32-bit VRAM output port (bits 19 to 17)
video output; 32-bit VRAM output port (bit16) GND7 (0 V) not connected
May 1993
6
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
SYMBOL VRO15 VRO14 VRO13 VRO12 n.c. VRO11 VRO10 VRO9 VRO8 VSS8 n.c. VDD8 VRO7 VRO6 VRO5 VRO4 n.c. VRO3 VRO2 VRO1 VRO0
PIN 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
STATUS O O O O - O O O O O - - O O O O - O O O O not connected GND8 (0 V) not connected +5 V supply voltage 8 not connected
DESCRIPTION
video output; 32-bit VRAM output port (bits 15 to 12)
video output; 32-bit VRAM output port (bits 11 to 8)
video output; 32-bit VRAM output port (bits 7 to 4)
video output; 32-bit VRAM output port (bits 3 to 0)
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7
Philips Semiconductors
Preliminary specification
Digital video scaler
6.1 Pin configuration
SAA7186
86 VRO10
83 VRO12
82 VRO13
100 VRO0
99 VRO1
97 VRO3
95 VRO4
98 VRO2
94 VRO5
93 VRO6
89 VSS8
87 VRO9
92 VRO7
90 n.c.
88 VRO8
96 n.c.
91 V DD8
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85 VRO11
84 n.c.
81 VRO14 80 VRO15 79 n.c. 78 VSS7 77 VRO16 76 VDD7 75 VRO17 74 VRO18 73 VRO19 72
LNQ
1
HREFD. 2 VSS1 i.c. VDD1 i.c. SP. AP n.c. 3 4 5 6 7 8 9
n.c.
UVIN0 10 UVIN1 11 UVIN2 12 UVIN3 13 VDD2 n.c. VSS2 14 15 16
71 VRO20 70 VRO21 69 VRO22 68 VRO23 67 V DD6
SAA7186
66 n.c. 65 V SS6 64 VRO24 63 VRO25 62 VRO26 61 VRO27 60
UVIN4 17 UVIN5 18 UVIN6 19 UVIN7 20 n.c. YIN0 YIN1 YIN2 YIN3 VDD3 n.c. VSS3 n.c. YIN4 21 22 23 24 25 26 27 28 29 30
31 41 49
n.c.
59 VRO28 58 VRO29 57 VRO30 56 VRO31 55 V DD5 54 n.c. 53 VSS5 52 n.c. 51 VCLK
INCADR 48
VS
VOEN 50
45
HREF 37
IICSA 46
40
RESN 43
34
36
44
VDD4
VSS4
BTST 47
39
33
CREF 35
YIN5
YIN6
32
YIN7
38
42
SDA
SCL
HFL
LLC
n.c.
n.c.
n.c.
MEH421
Fig.2 Pin configuration.
May 1993
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Philips Semiconductors
Preliminary specification
Digital video scaler
7 FUNCTIONAL DESCRIPTION 7.2 Decimation filters
SAA7186
The input port is output of Philips digital video multistandard decoders (SAA7151B, SAA7191B) or other similar sources. The SAA7186 input supports the 16-bit YUV 4:2:2 format. The video data from the input port are converted into a unique internal two's complement data stream and are processed in horizontal direction in two separate decimation filters. Then they are processed in vertical direction by the vertical processing unit (VPU). Chrominance data are interpolated to a 4:4:4 format; a chroma keying bit is generated. The 4:4:4 YUV data are then converted from the YUV to the RGB domain in a digital matrix. ROM tables in the RGB data path can be used for anti-gamma correction of gamma-corrected input signals. Uncorrected RGB and YUV signals can be bypassed. A scale control unit generates reference and gate signals for scaling of the processed video data. After data formatting to the various VRAM port formats, the scaled video data are buffered in the 16 word x 32-bit output FIFO register. The FIFO output is directly connected to the VRAM output bus VRO(31-0). Specific reference signals support an easy memory interfacing. All functions of the SAA7186 are controlled via I2C-bus using 17 subaddresses. The external microcontroller can get information by reading the status register. 7.1 Video input port
The decimation filters perform accurate horizontal filtering of the input data stream. Signal characteristics are matched in front of the pixel decimation stage, thus disturbing artifacts, caused by the pixel dropping, are reduced. The signal bandwidth can be reduced in steps of: 2-tap filter = -6 dB at 0.325 pixel rate 3-tap filter = -6 dB at 0.25 pixel rate 4-tap filter = -6 dB at 0.21 pixel rate 5-tap filter = -6 dB at 0.125 pixel rate 9-tap filter = -6 dB at 0.075 pixel rate The different characteristics are chosen dependent on the defined scaling parameters in an adaptive filter mode (AFS-bit = 1). The filter characteristics can also be selected independently by control bits HF2 to HF0 at AFS-bit = 0. 7.3 Vertical filters
The 16-bit YUV input data in 4:2:2 format (Table 1) consist of 8-bit luminance data Y (pins YIN(7-0)) and 8-bit time-multiplexed colour-difference data UV (pins UVIN(7-0)). The input data are clocked in by the signals LLC and CREF (Fig.3). HREF and VS inputs define the video scan pattern (window). Sequential input data * are limited to maximum 768 active pixels per line if the vertical filter is active * UV can be processed in straight binary and two's complement representation (controlled by TCC)
Y and UV data are handled in separate filters (Fig.1). Each of the two line memories has a capacity of 2 x 768 x 8-bit. Thus two complete video lines of 4:2:2 YUV data can be stored. The VPU is split into two memory banks and one arithmetic unit. The available processing modes, respectively transfer functions, are selectable by the bits VP1 and VP0 if AFS = 0. An adaptive mode is selected by AFS = 1. Disturbing artifacts, generated by line dropping, are reduced. Adaptive filter selection (AFS = 1): SCALING RATIO XD/XS 1 14/15 11/15 7/15 3/15 YD/YS 1 13/15 4/15 FILTER FUNCTION (REFER TO I2C SECTION) horizontal bypassed filter 1 filter 6 filter 3 filter 4 vertical bypassed filter 1 filter 2
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Philips Semiconductors
Preliminary specification
Digital video scaler
7.4 RGB matrix 7.5 Chrominance signal keyer
SAA7186
Y data and UV data are converted after interpolation into RGB data according to CCIR601 recommendation. Data are bypassed in YUV or monochrome modes. Table 1 4 : 2 : 2 format (pixels per line). The time frames are controlled by the HREF signal. PIXEL BYTE SEQUENCE Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 0 0 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 1 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 2 2 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 3 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 4 4
INPUT YIN7 YIN6 YIN5 YIN4 YIN3 YIN2 YIN1 YIN0 UVIN7 UVIN6 UVIN5 UVIN4 UVIN3 UVIN2 UVIN1 UVIN0 Y frame UV frame Note
The keyer generates an alpha signal to achieve a 5-5-5 + RGB alpha output signal. Therefore, the processed UV data amplitudes are compared with thresholds set via I2C-bus (subaddresses "0C to 0F"). A logical "1" signal is generated if the amplitude is inside the specified amplitude range, otherwise a logical "0" is generated. Keying can be switched off by setting the lower limit higher than the upper limit ("0C or 0E" and "0D or 0F"). 7.6 Scale control and vertical regions
The scale control block SC includes vertical address/sequence counters to define the current position in the input field and to address the internal VPU memories. To perform scaling, XD of XS pixel selection in horizontal direction and YD of YS line selection in vertical direction are applied. The pixel and line dropping are controlled at the input of the FIFO register. To control the decimation filter function and the vertical data processing in the adaptive mode (AFS = 1), the scaling ratio in horizontal and vertical direction is estimated in the SC block. The input field can be divided into two vertical regions - the bypass region and the scaling region, which are defined via I2C-bus by the parameters VS, VC, YO and YS. Vertical bypass region: Data are not scaled and independent of I2C-bits FS1, FS0 the output format is always 8-bit greyscale (monochrome). The SAA7186 outputs all active pixels of a line, defined by the HREF input signal if the vertical bypass region is active. This can be used, for example, to store videotext information in the field memory. The start line of the bypass region is defined by VS; the number of lines to be bypassed is defined by VC. Vertical scaling region: Data is scaled with start at line YO and the output format is selected when FS1, FS0 are valid. This is the "normal operation" area. The input/output screen dimensions in horizontal and vertical direction are defined by the parameters XO, XS and XD for horizontal YO, YS and YD for vertical. The circuit processes XS samples of a line. Remaining pixels are ignored if a line is longer than XS. If a line is
1. e = even pixel; o = odd pixel The matrix equations are these considering the digital quantization: R = Y + 1.375 V G = Y - 0.703125 V - 0.34375 U B = Y + 1.734375 U. Anti-gamma ROM tables: ROM tables are implemented at the matrix output to provide anti-gamma correction of the RGB data. A curve for a gamma of 1.4 is implemented The tables can be used (RTB-bit = 0) to compensate gamma correction for linear data representation of RGB output data.
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Philips Semiconductors
Preliminary specification
Digital video scaler
shorter than XS, processing is aborted when the falling edge of HREF is detected. Vertical regions in Fig.4: * the two regions can be programmed via I2C-bus, whereby regions should not overlap (active region overrides the bypass region). * the start of a normal active picture depends on video standard and has to be programmed to the correct value.
SAA7186
* the offsets XO and YO have to be set according to the internal processing delays to ensure the complete number of destination pixels and lines (Table 6). * the scaling parameters can be used to perform a panning function over the video frame/field.
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LLC
CREF
HREF
start of active line
Byte numbers for pixles: Y signal 0 1 2 3 4 5 6 7
U and V signal
U0
V0
U2
V2
U4
V4
U6
V6
MEH411
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LLC
CREF
HREF Byte number for pixels: Y signal n-5 n-4 n-3 n-2 n-1
end of active line
n
U and V signal
Un-5
Vn-5
Un-3
Vn-3
Un-1
Vn-1
MEH410
Fig.3 Horizontal and data multiplex timing.
May 1993
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Philips Semiconductors
Preliminary specification
Digital video scaler
7.7 Output data representation and levels
SAA7186
The signal levels of the RGB formats are limited in 8-bit to "0" or "255". For the 5-bit RGB formats a truncation from 8-bit to 5-bit is implemented. Fill values are inserted dependent on longword position and destination size: * "0" in RGB formats and for Y two's complement U, V * "128" for U, V (straight binary) * "255" in 8-bit greyscale format The unused output values of the YUV and greyscale formats can be used for other purposes.
Output data representation of the YUV data can be modified by bit MCT (subaddress 10). The DC gain is 1 for YUV input data. The corresponding RGB levels are defined by the matrix equations. The luminance levels are limited according to CCIR 601 16 (239) = black 235 (20) = white (..) = greyscale luminance levels if the YUV or monochrome luminance output formats are selected.
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vertical sync
vertical blanking VS YO
first valid line
vertical bypass start bypass region vertical bypass count equals VS
scaling region start scaling region scaling region count equals YS Y-size source
MEH357-1
Fig.4 Vertical regions.
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Philips Semiconductors
Preliminary specification
Digital video scaler
Table 2
SAA7186
VRAM port output data formats at EFE-bit = 0 dependent on FS1 and FS0 bits (set via I2C-bus) FS1 = 0; FS0 = 0 RGB 5-5-5 + 1 32-BIT WORDS n R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 n+1 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 n+2 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 n+3 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 n+4 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 n+5 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 n Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 n+1 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 FS1 = 0; FS0 = 1 YUV 4:2:2 32-BIT WORDS n+2 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 n+3 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 n+4 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 n+5 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 n Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 FS1 = 1; FS0 = 0 YUV 4:2:2 TEST 16-BIT WORDS n+1 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 n+2 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 FS1 = 1; FS0 = 1 8-BIT MONOCHROME 32-BIT WORDS n n+1 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0 n+2 n+3 Yc7 Yc6 Yc5 Yc4 Yc3 Yc2 Yc1 Yc0 Yd7 Yd6 Yd5 Yd4 Yd3 Yd2 Yd1 Yd0 n+4 n+5 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0 n+6 n+7 Yc7 Yc6 Yc5 Yc4 Yc3 Yc2 Yc1 Yc0 Yd7 Yd6 Yd5 Yd4 Yd3 Yd2 Yd1 Yd0 n+8 n+9 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0 n+10 n+11 Yc7 Yc6 Yc5 Yc4 Yc3 Yc2 Yc1 Yc0 Yd7 Yd6 Yd5 Yd4 Yd3 Yd2 Yd1 Yd0
PIXEL OUTPUT BITS PIXEL ORDER VRO31 VRO30 VRO29 VRO28 VRO27 VRO26 VRO25 VRO24 VRO23 VRO22 VRO21 VRO20 VRO19 VRO18 VRO17 VRO16 PIXEL ORDER VRO15 VRO14 VRO13 VRO12 VRO11 VRO10 VRO9 VRO8 VRO7 VRO6 VRO5 VRO4 VRO3 VRO2 VRO1 VRO0 Note
OUTPUTS NOT USED X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
1. = keying bit; R, G, B, Y, U and V = digital signals; e = even pixel number; o = odd pixel number; a b c d = consecutive pixels
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Philips Semiconductors
Preliminary specification
Digital video scaler
Table 3
SAA7186
VRAM port output data formats at EFE-bit = 1 dependent on FS1 and FS0 bits (set via I2C-bus) FS1 = 0; FS0 = 0 RGB 5-5-5 + 1 16-BIT WORDS n R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 n X X X X X X X X O/E VGT HGT X HRF LNQ PXQ n+1 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 n+1 X X X X X X X X O/E VGT HGT X HRF LNQ PXQ n+2 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 n+2 X X X X X X X X O/E VGT HGT X HRF LNQ PXQ n Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 n X X X X X X X X O/E VGT HGT X HRF LNQ PXQ FS1 = 0; FS0 = 1 YUV 4:2:2 16-BIT WORDS n+1 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 n+1 X X X X X X X X X O/E VGT HGT X HRF LNQ PXQ n+2 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 n+2 X X X X X X X X O/E VGT HGT X HRF LNQ PXQ n R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 n B7 B6 B5 B4 B3 B2 B1 B0 O/E VGT HGT X HRF LNQ PXQ FS1 = 1; FS0 = 0 RGB 8-8-8 24-BIT WORDS n+1 R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 n+1 B7 B6 B5 B4 B3 B2 B1 B0 O/E VGT HGT X HRF LNQ PXQ n+2 R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 n+2 B7 B6 B5 B4 B3 B2 B1 B0 O/E VGT HGT X HRF LNQ PXQ FS1 = 1; FS0 = 1 8-BIT MONOCHROME 16-BIT WORDS n n+1 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0 n n+1 X X X X X X X X O/E VGT HGT X HRF LNQ PXQ n+2 n+3 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0 n+2 n+3 X X X X X X X X O/E VGT HGT X HRF LNQ PXQ n+4 n+5 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0 n+4 n+5 X X X X X X X X O/E VGT HGT X HRF LNQ PXQ
PIXEL OUTPUT BITS PIXEL ORDER VRO31 VRO30 VRO29 VRO28 VRO27 VRO26 VRO25 VRO24 VRO23 VRO22 VRO21 VRO20 VRO19 VRO18 VRO17 VRO16 PIXEL ORDER VRO15 VRO14 VRO13 VRO12 VRO11 VRO10 VRO9 VRO8 VRO7 (2, 3) VRO6 (3) VRO5 (3) VRO4 (3) VRO3 VRO2 (3) VRO1 (3) VRO0 (3) Notes
1. = keying bit; R, G, B, Y, U and V = digital signals; e = even pixel number; o = odd pixel number; a b c d = consecutive pixels; O/E = odd/even flag 2. YUV 16-bit format: the keying signal is defined only for YU time steps. The corresponding YV sample has also to be keyed. The signal in monochrome mode can be used only in the transparent mode (TTR = 1), in this case Ya = Yb. 3. Data valid only when transparent mode active (TTR-bit = 1) and VCLK pin connected to LLC/2 clock rate. May 1993 14
Philips Semiconductors
Preliminary specification
Digital video scaler
7.8 Output FIFO register and VRAM output port
SAA7186
combination with INCADR to indicate the line increments (Figures 6 and 7). * INCADR output signal is used in combination with HFL to control horizontal and vertical address generation for a memory controller. The pulse sequence depends on field formats (interlace/ non-interlace or odd/even fields, Figures 6 and 7) and control bits OF (subaddress 00). HFL = 1 at the rising edge of INCADR: the end of line is reached, request for line address increment HFL = 0 at the rising edge of INCADR: the end of field/frame is reached, request for line and pixel addresses reset (The distance from the last half-full request HFL to the INCADR pulse may be longer than 64 x LLC. The HFL state is defined for minimum 4 x LLC in front of the rising edge of INCADR and minimum 2 x LLC afterwards.) * VCLK input signal to clock the FIFO register output data VRO(n). New data are placed on the VRO(n) port with the rising edge of VCLK (Fig.5). * VOEN input enables output data VRO(n). The outputs are in 3-state mode at VOEN = HIGH. VOEN changes only when VCLK is LOW. If VCLK pulses are applied during VOEN = HIGH, the outputs remain inactive, but the FIFO register accepts the pulses. 7.11 Transparent data transfer mode
The output FIFO register is the buffer between the video data stream and the VRAM data input port. Resized video data are buffered and formatted. 32-, 24- and 16-bit video data modes are supported. The various formats are selected by the bits EFE, FS1 and FS0. VRAM port formats are shown in Tables 2 and 3. The FIFO register capacity is 16 word x 32 bit (for 32-, 24-, or 16-bit video data). The bits LW1 and LW0 can be used to define the position of the first pixel each line in the 32-bit longword formats or to shift the UV sequence to VU in the 16-bit YUV formats (LW1 = 1). VRAM port inputs are: VCLK to clock the FIFO register output data and VOEN to enable output data. VRAM port outputs are: the HFL flag (half-full flag), the signal INCADR (refer to section "data burst transfer") and the reference signals for pixel and line selection on outputs VRO(7-0) (only for 24and 16-bit video data formats refer to "transparent data transfer"). 7.9 VRAM port transfer procedures
Data transfer on the VRAM port can be done asynchronously controlled by outputs HFL, INCADR and input VCLK (data burst transfer with bit TTR = 0). Data transfer on the VRAM port can be done synchronously controlled by output reference signals on outputs VRO(7-0) and a clock rate of LLC/2 on input VCLK (transparent data transfer with bit TTR = 1 and EFE = 1). The scaling capability of the SAA7186 can be used in various applications. 7.10 Data burst transfer mode
Data transfer on the VRAM port is asynchronously (TTR = 0). This mode can be used for all output formats. Four signals for communication with the external memory are provided. * HFL flag, the half-full flag of the FIFO output register is raised when the FIFO contains at least 8 data words (HFL = HIGH). By setting HFL = 1, the SAA7186 requests a data burst transfer by the external memory controller, that has to start a transfer cycle within the next 32 LLC cycles for 32-bit longword modes (16 LLC cycles for 16- and 24-bit modes). If there are pixels in the FIFO at the end of a line, which are not transferred, the circuit fills up the FIFO register with "fill pixels" until it is half-full and sets the HFL flag to request a data burst transfer. After transfer is done, HFL is used in May 1993 15
Data transfer on the VRAM port can be achieved synchronously (TTR = 1). With a continuous clock rate of LLC/2 on input VCLK, the SAA7186 delivers a continuously processed data stream. Therefore, the extended formats of the VRAM output port have to be selected (bit EFE = 1; Table 3). The reference and gate signals on outputs VRO(6-1) and the LNQ signal are delivered in each field (means scaled and ignored fields). The PXO signal (also VRO0) is only delivered in active fields. The output signals VRO(7-0) can be used to buffer qualified pre-processed RGB or YUV video data (notice: the YUV data are only valid in qualified time slots). Control output signals in Table 3 are:
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
O/E VGT
keying signal of the chroma keyer odd/even field bit according to the internal field processing vertical gate signal, "1" marks the scaling window in vertical direction from YO to (YO + YS) lines, cut by VS.
HGT horizontal gate signal, "1" marks horizontal direction from XO to (XO + XS) lines, cut by HREF. HRF LNQ delay compensated horizontal reference signal. line qualifier signal, active polarity is defined by QPL bit.
PXQ pixel qualifier signal, active polarity is defined by QPP bit. 7.12 Power-on reset
* the FIFO register contents are undefined * outputs VRO are set to high-impedance state * output INCADR = HIGH * output HFL = LOW until the VPE bit is set to "1" * subaddress "10" is set to 00h and VPE-bit in subaddress "00" is set to zero (Table 4).
May 1993
16
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
handbook, full pagewidth
PIXCLK (LLC/2)
FIFO memory filling level
6
7
8
7
7
6
5
5
4
3
3
HFL min. 8 samples available in FIFO max. 32LLC (16 PIXCLK VCLK 1 transfer cycle (8 VCLK cycles) VOEN
VRO(n)
7
0
1
2
3
4
5
6
7
MEH407
Fig.5
Output port transfer to VRAM at 32-bit data format without scaling. If VCLK cycles occur at VOEN = HIGH, the FIFO register is unchanged, but the outputs VRO(31-0) remain in 3-state position.
handbook, full pagewidth
line n active video
line n+1 vertical blanking
internal signal
last half-full request for line n (1) HFL 64LLC
min. set-up time
INCADR (1) pulse only at interlace scan
min. 64LLC 10LLC
(1) line increment (VRAM) only in odd field vertical reset
MEH406
Fig.6 Vertical reset timing to the VRAM.
May 1993
17
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
handbook, full pagewidth
line n active video
line n+1 horizontal blanking active video first half-full request for line n+1
internal signal
last half-full request for line n (1) HFL 6LLC 6LLC INCADR min. 64LLC 64LLC 2LLC 10LLC min. set-up time
(1)
(1) pulse only at interlace scan
line increment (VRAM)
MEH405-1
Fig.7 Horizontal increment timing to the VRAM.
Fig.8 Reference signals for scaling window.
May 1993
18
Philips Semiconductors
Preliminary specification
Digital video scaler
7.13 Field processing 8 OPERATION CYCLE
SAA7186
The phase of the field sequence (odd/even dependent on inputs HREF and VS) is detected by means of the falling edge of VS. The current field phase is reported in the status byte by the OEF bit (Table 5). OEF bit can be stable 0 or 1 for non-interlaced input frames or non standard input signals VS and/or HREF (nominal condition for VS and HREF - SAA7191 B with active vertical noise limiter). A free-running odd/even flag is generated for internal field processing if the detection reports a stable OEF bit. The POE bit (subaddress 0B) can be used to change the polarity of the internal flag (in case of non-standard VS and HREF signals) to control the phase of the free-running flag, and to compensate mis-detections. Thus, the SAA7186 can be used under various VS/HREF timing conditions. The SAA7186 operates on fields. To support progressive displays and to avoid movement blurring and artifacts, the circuit can process both or single fields of interlaced or non-interlaced input data. Therefore the OF bits can be used. The bits OF1 and OF0 (Table 6) determine the INCADR/HFL generation in "data burst transfer mode". One of the fields (odd or even) is ignored when OF1 = 1; then no line increment sequence (INCADR/HFL) is generated, the vertical reset pulse is only generated. With OF1 = OF0 = 0 the circuit supports correct interlaced data storage. Two INCADR/HFL sequences are generated in each qualified line; additionally an INCADR/HFL sequence after the vertical reset sequence of an odd field is generated. Thereby, the scaled lines are automatically stored in the right sequence.
The operation is synchronized by the input field. The cycle is specified in the flow chart (Fig.9). The circuit is inactive after power-on reset, VPO is 0 and the FIFO control is set "empty". The internal control registers are updated with the falling edge of VS signal. The circuit is switched active and waits for a transmission of VS and a vertical reset sequence to the memory controller. Afterwards, the circuit waits for the beginning of a scaling or bypass region. The processing of a current line is finished when a vertical sync pulse appears. The circuit performs a coefficient update and generates a new vertical reset (if it is still active). Line processing starts when a line is decided to be active, the circuit starts to scale it. Active pixels are loaded into the FIFO register. An HFL flag is generated to initialize a data transfer when eight words are completed. The line end is reached when the programmed pixel number is processed or when a horizontal sync pulse occurs. If there are pixels in the FIFO register, it is filled up until it is half-full to cause a data transfer. Horizontal increment pulses are transmitted after this data transfer. Remarks: The SAA7186 will always wait for the HREF/VS pulse before the line increment/vertical reset sequence is performed. After each line/field, the FIFO control is set to empty when INCADR/HFL sequence is transmitted. No additional actions are necessary if the memory controller has ignored the HFL signal. There is no need to handle overflow/underflow of the FIFO register.
May 1993
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Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
handbook, full pagewidth
EXTERNAL RESET, VPE = 0
VERTICAL SYNC DETECTED ? YES
NO
COEFFICIENT UPDATE
VPE = 1 ?
NO
YES DO VERTICAL RESET
YES
VERTICAL SYNC DETECTED ? NO
YES
CURRENT LINE IN ACTIVE REGION ?
NO
CURRENT LINE IN BYPASS REGION ? YES SET SCALING ACTIVE IN CONTROL STAGE SET BYPASS MODE IN CONTROL STAGE
NO
PROCESS A LINE
MGL119
Fig.9 Operation cycle
May 1993
20
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
handbook, full pagewidth
CVBS
ADC
TDA8708A
digital CVBS
DMSD
SAA7151B/91B
YUV format 4.2:2 HREF / VS
RGB/YUV
DVS
SAA7186
RAM
VIDEO GRAPHICS control
display data
LLC / CREF LFCO HFL INCADR
address
SCGC
SAA7157/97
VCLK VOEN
MEMORY CONTROLLER
BUFFER data bus CPU address / control bus
system clock
SYSTEM RAM
MEH554
Fig.10 SAA7186 system configuration in Data Burst Transfer Mode (TTR = , VCLK = continuous).
handbook, full pagewidth
YUV format 4.2:2 digital CVBS
RGB/YUV
(VRO(31-8)) qualifier and SAA7186 references (VRO(7-0))
CVBS
ADC
TDA8708A
DMSD
SAA7151B/91B HREF / VS
DVS
FIFO BUFFER
RAM
VIDEO GRAPHICS control
display data
LLC / CREF write LFCO VOEN = 1 read
address
SCGC
SAA7157/97
LLC2
INV
VCLK = LLC2
MEMORY CONTROLLER
MEH555
Fig.11 SAA7186 system configuration in Transparent Data Transfer Mode (TTR = 1, EFE = 1, VCLK = continuous (_LLC2)).
May 1993
21
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
handbook, full pagewidth
(a) 1st field input CVBS
625
1
2
3
4
5
6
7
8
9
HREF 541 x 2/LLC VS
(b) 2nd field input CVBS
313
314
315
316
317
318
319
320
321
HREF
VS
69 x 2/LLC
50 Hz
handbook, full pagewidth
MEH412
(a) 1st field input CVBS
525
1
2
3
4
5
6
7
8
9
HREF 449x 2/LLC VS
ODD
2 x 2/LLC
(b) 2nd field input CVBS
263
264
265
266
267
268
269
270
271
HREF 59 x 2/LLC VS 2 x 2/LLC ODD
60 Hz
Fig.12 VS timing for video input source SAA7191B.
MEH225-1
May 1993
22
Philips Semiconductors
Preliminary specification
Digital video scaler
9 S I2C-BUS FORMAT SLAVE ADDRESS A SUBADDRESS A DATA0 A DATAn
SAA7186
A
P
S SLAVE ADDRESS A SUBADDRESS(1) DATA P X
= = = = = = =
start condition 1011 100X (IICSA = LOW) or 1011 110X (IICSA = HIGH) acknowledge, generated by the slave subaddress byte (Table 4) data byte (Table 4) stop condition read/write control bit X = 0, order to write (the circuit is slave receiver) X = 1, order to read (the circuit is slave transmitter)
Note 1. If more than 1 byte DATA are transmitted, then auto-increment of the subaddress is performed.
May 1993
23
Philips Semiconductors
Preliminary specification
Digital video scaler
Table 4 I2C-bus; subaddress and data bytes for writing (X in address byte = 0). DATA FUNCTION SUBADDRESS D7 Formats and sequence Output data pixel/line continued in Input data pixel/line continued in Horizontal window start Pixel decimation filter Output data lines/field continued in Input data lines/field continued in Vertical window start AFS/vertical processing Vertical bypass start continued in Vertical bypass count continued in Chroma keying lower limit for V upper limit for V lower limit for U upper limit for U Byte 10(2) Unused Notes 1. Default register contents fill in by hand 2. Byte 10 is set to 00h after power-on reset. 0C 0D 0E 0F 10 11 to 1F VL7 VU7 UL7 UU7 0 VL6 VU6 UL6 UU6 0 VL5 VU5 UL5 UU5 0 VL4 VU4 UL4 UU4 MCT VL3 VU3 UL3 UU3 QPL VL2 VU2 UL2 UU2 QPP VL1 VU1 UL1 UU1 TTR 00 01 04 02 04 03 04 05 09 06 09 07 08 09 0B 0A 0B VC7 TCC VC6 0 VC5 0 YO7 AFS VS7 YO6 VP1 VS6 YO5 VP0 VS5 YO4 YO8 VS4 VS8 VC4 VS8 VC3 0 VC2 VC8 VC1 0 YS7 YS6 YS5 YS4 YS3 YS9 YO3 YS9 VS3 YS2 YS8 YO2 YS8 VS2 YO1 YD9 VS1 XO7 HF2 YD7 XO6 HF1 YD6 XO5 HF0 YD5 XO4 XO8 YD4 XS7 XS6 XS5 XS4 XS3 XS9 XO3 XS9 YD3 XS2 XS8 XO2 XS8 YD2 XO1 XD9 YD1 YD9 YS1 RTB XD7 D6 OF1 XD6 D5 OF0 XD5 D4 VPE XD4 D3 LW1 XD3 D2 LW0 XD2 D1 FS1 XD1 XD9 XS1
SAA7186
D0 FS0 XD0 XD8 XS0 XO0 XD8 YD0 YD8 YS0 YO0 YD8 VS0 VC0 POE VL0 VU0 UL0 UU0 EFE
DF(1) tbf
May 1993
24
Philips Semiconductors
Preliminary specification
Digital video scaler
Table 5 I2C-bus status byte (X in address byte = 1) DATA FUNCTION D7 status byte Function of status bits: ID3 to ID0 Software version of SAA7186 compatible with ID3 0 OEF SVP ID2 0 ID1 0 ID0 1 version 1 ID3 D6 ID2 D5 ID1 D4 ID0 D3 0 D2 0
SAA7186
D1 OEF
D0 SVP
Identification of field sequence dependent on inputs HREF and VS: 0 = even field detected; 1 = odd field detected State of VRAM port: 0 = inputs HFL and INCADR inactive; 1 = inputs HFL and INCADR active.
May 1993
25
Philips Semiconductors
Preliminary specification
Digital video scaler
Table 6 "00" RTB Function of the register bits of Table 4 ROM table bypass switch: 0 = anti-gamma ROM active 1 = table is bypassed
SAA7186
-------------- ------------------------------------------------ OF1 to OF0 Set output field mode: OF1 0 0 1 1 VPE OF0 0 1 0 1 field mode DVS process both fields for interlaced storage both fields for non-interlaced storage odd fields only (even fields ignored) for non-interlaced storage even fields only (odd fields ignored) for non-interlaced storage 0 = HFL and INCADR inactive; VRO outputs in 3-state position (HFL = LOW, INCADR = HIGH) 1 = HFL and INCADR enabled; VRO outputs dependent on VOEN
-------------- -------------------------------------------------- VRAM port outputs enable:
-------------- ------------------------------------------------ LW1 to LW0 First pixel position in VRO data for FS1 = 0; FS0 = 0 (RGB) and FS1 = 0; FS0 = 1 (YUV):
LW1 LW0
31 to 24 pixel 0 pixel 0 black black 31 to 24 pixel 0 black black black pixel 0 black pixel 0 black
23 to 16 pixel 0 pixel 0 black black 23 to 16 pixel 1 pixel 0 black black pixel 1 pixel 0 pixel 1 pixel 0
15 to 8 pixel 1 pixel 1 pixel 0 pixel 0 15 to 8 pixel 2 pixel 1 pixel 0 black X X X X
7 to 0 pixel 1 pixel 1 pixel 0 pixel 0 7 to 0 pixel 3 pixel 2 pixel 1 pixel 0 X X X X ) ) EFE = 0, TRR = 0 ) ) ) EFE = 1, TRR = 0; ) LW only effects ) greyscale format ) ) ) EFE = 0, TRR = 0 ) )
0 0 1 1
LW1
0 1 0 1
LW0
First pixel position in VRO data for FS1 = 1; FS0 = 1 (monochrome): 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
May 1993
26
Philips Semiconductors
Preliminary specification
Digital video scaler
FS1 to FS0 FIFO output register format select (EFE-bit see "10"): EFE 0 0 0 0 FS1 FS0 0 0 1 1 0 1 0 1 output format (Tables 2 and 3)
SAA7186
RGB 5-5-5 + alpa; 2x16-bit/pixel; 32-bit word length; RGB matrix on, VRAM output format YUV 4:2:2; 2x16-bit/pixel; 32-bit word length; RGB matrix off, VRAM output format YUV 4:2:2; video test mode; 1x16-bit/pixel; 16-bit word length; RGB matrix off, optional output format monochrome mode; 4x8-bit/pixel; 32-bit word length; RGB matrix off, VRAM output format RGB 5-5-5 + alpa; 1x16-bit/pixel; 16-bit word length; RGB matrix on, VRAM output + transparent format YUV 4:2:2 + alpa; 1x16-bit/pixel; 16-bit word length; RGB matrix off, VRAM output + transparent format RGB 8-8-8 + alpa; 1x24-bit/pixel; 24-bit word length; RGB matrix on, VRAM output + transparent format monochrome mode; 2x8-bit/pixel; 16-bit word length; RGB matrix off, VRAM output + transparent format
1 1 1 1 "01 and 04" XD9 "02 and 04" XS9 "03 and 04" XO8 to XO0 to XS0 to XD0
0 0 1 1
0 1 0 1
Pixel number per line (straight binary) on output (VRO): 00 0000 0000 to 11 1111 1111 (number of XS pixels as a maximum) Pixel number per line (straight binary) on inputs (YIN and UVIN): 00 0000 0000 to 11 1111 1111 (number of input pixels per line as maximum) Horizontal start position (straight binary) of scaling window (take care of active pixel number per line). start with 1st pixel after HREF rise = 0 0001 0000 to 1 1111 1111 (010 to 1FF) window start and window end may be cut by internal delay compensated HREF = 0 phase. XO has to be matched to the internal processing delay to get full scaling range
May 1993
27
Philips Semiconductors
Preliminary specification
Digital video scaler
"04" HF2 to HF0 Horizontal decimation filter (Figures 13 and 14): HF2 HF1 0 0 0 0 1 1 1 1 "05 and 08" YD9 "06 and 08" YS9 to YS0 Line number per input field (straight binary): 00 0000 0000 11 1111 1111 "07 and 08" YO8 to YO0 to YD0 Line number per output field (straight binary): 00 0000 0000 to 11 1111 1111 (number of YS lines as a maximum) 0 0 1 1 0 0 1 1 HF0 0 1 0 1 0 1 0 1 taps filter 2 3 5 9 1 1 8 4
SAA7186
filter 1 (1/2 (1 + z-1)) filter 2 (1/4 (1 + 2z-1 + z-2)) filter 3 (1/8 (1 + 2z-1 + 2z-2 + 2z-3 + z-4)) filter 4 (1/16 (1 + 2z-1 + 2z-2 + 2z-3 + 2z-4 + 2z-5 + 2z-6 + 2z-7 + z-8)) filter bypassed filter bypassed + delay in Y channel of 1T filter 5 (1/16 (1 + 3z-1 + 3z-2 + z-3 + z-4 + 3z-5 + 3z-6 + z-7)) (1/8 (1 + 3z-1 + 3z-2 + z-3))
0 line 1023 lines (maximum = number of lines/field - 3)
Vertical start of scaling window. "0" equals 3rd line after rising slope of VS input signal. Take care of active line number per field (straight binary). 0 0000 0000 start with 3rd line after the rising slope of VS 0 0000 0011 start with 1st line after the falling slope of nominal VS (SAA7151B/91B) 1 1111 1111 511 + 3 lines after the rising slope of VS (maximum value) Adaptive filter switch: 0 = off; use VP1, VP0 and HF2 to HF0 bits 1 = on; filter characteristics are selected by the scaler
"08" AFS
-------------- ------------------------------------------- VP1 to VP0 Vertical data processing VP1 VP0 0 0 1 1 "09 and 0B" VS8 to VS0 Vertical bypass start, sets begin of the bypass region (straight binary). Scaling region overrides bypass region (YO bits): 0 0000 0000 start with 3rd line after the rising slope of VS 0 0000 0011 start with 1st line after the falling slope of nominal VS (SAA7151B/91B) 1 1111 1111 511 + 3 lines after the rising slope of VS (maximum value) 0 1 0 1 processing bypassed delay of one line H(z) = z-H vertical filter 1: (H(z) = 1/2 (1 + z-H)) vertical filter 2: (H(z) = 1/4 (1 + 2z-H + z-2H))
May 1993
28
Philips Semiconductors
Preliminary specification
Digital video scaler
"0A and 0B" VC8 to VC0 Vertical bypass count, sets length of bypass region (straight binary): 00 0000 0000 11 1111 1111 TCC
SAA7186
0 line length 511 lines length (maximum = number of lines/field - 3) 0 = binary input data 1 = two's complement input data
-------------- ------------------------------------------------ Two's complement input data select (U, V):
-------------- ----------------------------------------------- POE "0C" VL7 to VL0 Set lower limit for V colour-difference signal (8 bit; two's complement): 1000 0000 0000 0000 0111 1111 "0D" VU7 to VU0 Set upper limit for V colour-difference signal (8 bit; two's complement): 1000 0000 0000 0000 0111 1111 "0E" UL7 to UL0 Set lower limit for U colour-difference signal (8 bit; two's complement): 1000 0000 0000 0000 0111 1111 "0F" UU7 to UU0 Set upper limit for U colour-difference signal (8 bit; two's complement): 1000 0000 0000 0000 0111 1111 as maximum negative value = -128 signal level limit = 0 as maximum positive value = +127 signal level as maximum negative value = -128 signal level limit = 0 as maximum positive value = +127 signal level as maximum negative value = -128 signal level limit = 0 as maximum positive value = +127 signal level as maximum negative value = -128 signal level limit = 0 as maximum positive value = +127 signal level Polarity, internally detected odd/even flag O/E: 0 = flag unchanged; 1 = flag inverted
May 1993
29
Philips Semiconductors
Preliminary specification
Digital video scaler
"10" MCT
SAA7186
Monochrome and two's complement output data select: 0 = inverse greyscale luminance (if greyscale is selected by FS bits) or straight binary U, V data output 1 = non-inverse monochrome luminance (if greyscale is selected by FS bits) or two's complement U, V data output Line qualifier polarity flag : 0 = LNQ is active-LOW (pin 1 and on VRO1, pin 99); 1 = LNQ is active-HIGH 0 = PXQ is active-LOW (VRO0, pin 100); 1 = PXQ is active-HIGH 0 = normal operation (VRAM protocol valid,) 1 = FIFO register transparent (output FIFO in shift register mode)
-------------- ------------------------------------------------ QPL
-------------- ---------------------------------------------- QPP Pixel qualifier polarity flag :
-------------- ------------------------------------------------ TTR Transparent data transfer:
-------------- ------------------------------------------------ EFE Extended formats enable, FS-bits in subaddress "00"
May 1993
30
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
handbook, full pagewidth
10
MEH514
(dB) 0 100, 101
-10
010 110 111 001 000
-20
011
-30 011 110 -50
-40
0
0.1
0.2
0.3
0.4
f / fClock
0.5
Fig.13 Horizontal frequency characteristic of luminance signal (Y) dependent on HF2 to HF0 bits (subaddress 04).
handbook, full pagewidth
10
MEH513
(dB) 0 100, 101
000 -10 111 010 -20 001
-30
011, 110
-40 011, 110 -50
0
0.05
0.10
0.15
0.20
f / fClock
0.25
Fig.14 Horizontal frequency characteristic of chrominance signals (UV) without UV interpolation dependent on HF2 to HF0 bits (subaddress 04).
May 1993
31
Philips Semiconductors
Preliminary specification
Digital video scaler
10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI IDD Ptot Tstg Tamb VESD Note 1. Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. 11 DC CHARACTERISTICS VDD1 to VDD8 = 4.5 to 5.5 V; Tamb = 0 to 70 C unless otherwise specified. SYMBOL VDD IP PARAMETER supply voltage range (pins 5, 14, 26, 40, 55, 67, 76 and 91) total supply current (IDD1 + IDD2 + IDD3 + IDD4 + IDD5 + IDD6 + IDD7 + IDD8) input voltage LOW input voltage HIGH input leakage current input capacitance VI L = 0 data clocks Data and control outputs VO L VO H IO off CO output voltage LOW output voltage HIGH note 1 note 1 - 2.4 - - -0.5 3 - acknowledge I44 = 3 mA 3 - - - - - - - - - - inputs LOW and outputs without load CONDITIONS MIN. 4.5 - 5 80 TYP. DC input voltage on all pins supply current (pins 5, 14, 26, 40, 55, 67, 76 and 91) total power dissipation storage temperature range operating ambient temperature range electrostatic handling(1) for all pins PARAMETER supply voltage (pins 5, 14, 26, 40, 55, 67, 76 and 91) MIN. -0.5 -0.5 - 0 -65 0 -
SAA7186
MAX. 6.5 VDD 70 1 150 70 2000
UNIT V V mA W C C V
MAX. 5.5 -
UNIT V mA
Data and control inputs VI L VI H ILI CI -0.5 2.0 - - - - - - - - 0.8 VDD+0.5 10 8 10 V V A pF pF
0.6 - 5 8
V V A pF
3-state outputs high-impedance output current high-impedance output capacitance
I2C-bus, SDA and SCL (pins 44 and 45) VI L VI H I44, 45 IACK VO L input voltage LOW input voltage HIGH input current output current on pin 44 output voltage at acknowledge 1.5 VDD+0.5 10 - 0.4 V V A mA V
May 1993
32
Philips Semiconductors
Preliminary specification
Digital video scaler
12 AC CHARACTERISTICS VDD1 to VDD8 = 4.5 to 5.5 V; Tamb = 0 to 60 C unless otherwise specified. SYMBOL LLC timing (pin 36) tLLC tp tr tf tSU tHD tVCLK tp L, tp H tr tf CL tOH tOHL tOHV tOD tODL tODV tD tE tHFL VOE tHFL VCLK Notes cycle time pulse width (duty factor) rise time fall time Fig.15 11 3 Fig.16 note 2 note 3 50 17 - - Figures 15 and 16 VRO outputs other outputs VRO data hold time related to LLC (INCADR, HFL) related to VCLK (HFL) VRO data delay time related to LLC (INCADR, HFL) related to VCLK (HFL) output disable time to 3-state output enable time from 3-state HFL maximum response time HFL maximum response time CL = 10 pF; note 4 CL = 10 pF; note 5 CL = 10 pF; note 5 CL = 40 pF; note 4 CL = 25 pF; note 5 CL = 25 pF; note 5 CL = 40 pF; note 6 CL = 40 pF; note 6 VRAM port enabled HFL set at beginning of VCLK burst 15 7.5 0 0 0 - - - - - - - - - - - - - - - - - - - - - - - tLLC H / tLLC PARAMETER CONDITIONS Fig.11 31 40 - - - 50 - - MIN. TYP.
SAA7186
MAX.
UNIT
45 60 5 6 - -
ns % ns ns
Input data and CREF timing setup time hold time
ns ns
VCLK timing (pin 51) VRAM port clock cycle time LOW and HIGH times rise time fall time
200 - 5 6
ns ns ns ns
Output data and reference signal timing load capacitance
40 25 - - - 25 60 60 40 40 810 840
pF pF ns ns ns ns ns ns ns ns ns ns
1. Levels are measured with load circuit. VRO outputs with 1.2 k in parallel to 25 pF at 3 V (TTL load). 2. Maximum tVCLK = 200 ns for test mode only. The applicable maximum cycle time depends on data format, horizontal scaling and input data rate. 3. Measured at 1,5 V level; tp L may be unlimited. 4. Timings of VRO refer to the rising edge of VLCK. 5. The timing of INCADR refers to LLC; the rising edge of HFL always refers to LLC. During a VRAM transfer is the falling edge of HFL generated by VCLK. Both edges of HFL refer to LLC during horizontal increment and vertical reset cycles. 6. Asynchronous signals with timing referring to the 1.5 V switching point of VOEN input signal (pin 50).
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Preliminary specification
Digital video scaler
SAA7186
handbook, full pagewidth
t LLC t LLC H 2.4 V
clock input LLC
1.5 V 0.6 V tf t SU tr
t HD 2.0 V
inputs CREF 0.8 V t SU t HD
2.0 V input data not valid 0.8 V t ODL
t OHL
2.4 V output HFL and INCADR not valid 0.6 V
MEH408-1
Fig.15 Data input timing (LLC).
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Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
handbook, full pagewidth
2.0 V VOEN 1.5 V 0.8 V
t VCLK tf VCLK tr 2.0 V 1.5 V 0.8 V t EN not valid output VRO(n) 0.6 V t ODV t OHV 2.4 V output HFL 0.6 V
MEH409
tp H t OD t OH
tp L
2.4 V
Fig.16 Data output timing (VCLK).
13 PROCESSING DELAYS PORTS YIN to VRO UVIN to VRO HREF to VRO 58 58 58 DELAY IN LLC REMARKS in transparent mode only in transparent mode only in transparent mode only
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Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
14 PROGRAMMING EXAMPLE Slave address byte is B8h at pin IICSA = 0 (or BCh at pin IICSA = +5 V). This example shows the setting via I2C-bus for the processing of a picture segment at 1:1 horizontal and vertical scale. Values in brackets [..]: If no scaling or panning is wanted, the parameters XD, XS, YD and YS should be set to the maximum value 3FFh. the parameters XO and YO should be set to the minimum value 000h. (in this case, HREF and VS from external define the SAA7186 processing window). SUBADDR. (HEX) 00 BITS RTB, OF(1:0), VPE, LW(1:0), FS(1:0), XD(7:0) XS(7:0) XO(7:0) HF(2:0), XO(8), XS(9, 8), XD(9, 8) YD(7:0) YS(7:0) YO(7:0) AFS, VP(1:0), YO(8), YS(9, 8), YD(9, 8) VS(7:0) VC(7:0) VS(8), VC(8), TCC, POE FUNCTION ROM table control and field sequence processing; VRAM port enable; output format select LSB's output pixel/line LSB's input pixel/line LSB's for horizontal window start horizontal filter select and MSB's of subaddresses 01, 02, 03 LSB's output lines/field LSB's input lines/field LSB's vertical window start adaptive and vertical filter select; MSB's of subaddresses 05, 06, 07 LSB's vertical bypass start position LSB's vertical bypass lines/field MSB's of subaddresses 09, 0A; UV input data representation and odd/even polarity switch UV keyer: lower limit V (R-Y) UV keyer: upper limit V (R-Y) UV keyer: lower limit U (B-Y) UV keyer: upper limit U (B-Y) Y or UV output data representation, output data transfer mode, pixel/ line qualifier polarity. VALUE (HEX) COMMENT
01 02 03 04 05 06 07 08 09 0A 0B
11 80 [FF] 80 [FF] 10 [00]
(1) 384 pixels out 384 pixels in 1st pixel after HREF = 1
85 [8F] 90 [FF] 90 [FF] 03 [00]
horizontal filter bypassed 144 lines out 144 lines in 1st line after VS = 0; (2) no adaptive select vertical filter bypassed not bypassed region defined; (3) (4)
00 [FF] 00 00 00
0C 0D 0E 0F 10
VL(7:0) VU(7:0) UL(7:0) UU(7:0) MCT, QPP, QPL, TTR, EFE
00 FF 00 00
) keying is switched off ) by VU < VL -
00
(5)
Notes 1. RTB = OF = VPE = LW = FS = 0 00 1 00 01 ROM table is active (only for RGB formats) SAA7186 processes the both fields for interlaced display VRAM port is enabled longword position of first pixel in each output line = 0 16-bit 4:2:2 YUV output format is selected straight binary UV input data expected
2. for nominal VS length of 6 x H-period (input SAA7191B respectively SAA7151B with active VNL) 3. TTC = 0
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Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
4. odd/even polarity unchanged - can be used to change the field sequence if phase relations between HREF and VS are not according to SAA7191B respectively SAA7151B specification 5. MCT = QPP = QPL = TTR = EFE = 0 0 0 0 0 when EFE, FS = 001h: UV output data are straight binary the pixel qualifier PXQ is "0"-active (if TTR, EFE = 1) line qualifier LNQ is "0"-active (if TTR, EFE = 1) VRAM port is set to data burst transfer 32-bit longword formats selected.
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Philips Semiconductors
Preliminary specification
Digital video scaler
15 PACKAGE OUTLINE QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SAA7186
SOT317-2
c
y X
80 81
51 50 ZE
A
e E HE A A2 A1
Q (A 3) Lp L detail X
wM pin 1 index bp 100 1 wM D HD ZD B vM B 30 vMA 31
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.40 0.25 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.65 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 Q 1.4 1.2 v 0.2 w 0.15 y 0.1 Z D (1) Z E(1) 0.8 0.4 1.0 0.6 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT317-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
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Philips Semiconductors
Preliminary specification
Digital video scaler
16 SOLDERING 16.1 Introduction 16.3 Wave soldering
SAA7186
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 16.2 Reflow soldering
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.4 Repairing soldered joints
Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C.
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
Digital video scaler
17 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7186
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 18 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 19 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Philips Semiconductors
Preliminary specification
Digital video scaler
NOTES
SAA7186
May 1993
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Philips Semiconductors
Preliminary specification
Digital video scaler
NOTES
SAA7186
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Philips Semiconductors
Preliminary specification
Digital video scaler
NOTES
SAA7186
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43
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
657027/00/01/pp44
Date of release: May 1993
Document order number:
9397 750 02436

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